//
// Copyright (c) Microsoft Corporation.  All rights reserved.
//
//
// Use of this sample source code is subject to the terms of the Microsoft
// license agreement under which you licensed this sample source code. If
// you did not accept the terms of the license agreement, you are not
// authorized to use this sample source code. For the terms of the license,
// please see the license agreement between you and Microsoft or, if applicable,
// see the LICENSE.RTF on your install media or the root of your tools installation.
// THE SAMPLE SOURCE CODE IS PROVIDED "AS IS", WITH NO WARRANTIES OR INDEMNITIES.
//
//
// (C) Copyright 2006 Marvell International Ltd.
// All Rights Reserved
//
/*
 * INTEL CONFIDENTIAL
 * Copyright 2005-2006 Intel Corporation All Rights Reserved.
 * 
 * The source code contained or described herein and all documents
 * related to the source code (Material) are owned by Intel Corporation
 * or its suppliers or licensors.  Title to the Material remains with
 * Intel Corporation or its suppliers and licensors. The Material contains
 * trade secrets and proprietary and confidential information of Intel
 * or its suppliers and licensors. The Material is protected by worldwide
 * copyright and trade secret laws and treaty provisions. No part of the
 * Material may be used, copied, reproduced, modified, published, uploaded,
 * posted, transmitted, distributed, or disclosed in any way without Intel's
 * prior express written permission.
 * 
 * No license under any patent, copyright, trade secret or other intellectual
 * property right is granted to or conferred upon you by disclosure or
 * delivery of the Materials, either expressly, by implication, inducement,
 * estoppel or otherwise. Any license under such intellectual property rights
 * must be express and approved by Intel in writing.
 */

/* 
 * xllp_ci.h
 *
 * xllp_ci driver for Monahans 
 *
 */

/*++

Module Name:  $Workfile: xllp_ci.h $

Abstract:  
      contains all Monahans QCI specific macros, typedefs, and prototypes.
    Declares no storage.

Notes:Only valid for processor code named Monahans.

--*/


#ifndef __XLLP_CI_H__
#define __XLLP_CI_H__

#ifdef __cplusplus
extern "C" {
#endif

//---------------------------------------------------------------------------
// Register definitions
//---------------------------------------------------------------------------
#define XLLP_CI_REGBASE_PHY 0x50000000

enum XLLP_CI_REGS {
        XLLP_CI_REG_SIZE = 0x04U,    // Size of each CI register (below) = 4 bytes 
                
        XLLP_CICR0   = 0x0000,           // Control
        XLLP_CICR1   = 0x0004,
        XLLP_CICR2   = 0x0008,
        XLLP_CICR3   = 0x000C,
        XLLP_CICR4   = 0x0010,
        
        XLLP_CISR    = 0x0014,           // Status
        XLLP_CITOR   = 0x001C,           // Time-out
        
        XLLP_CIBR0   = 0x0028,           // Receive Buffer
        XLLP_CIBR1   = 0x0030,
        XLLP_CIBR2   = 0x0038,
        XLLP_CIBR3   = 0x0040,
        XLLP_CIRCD   = 0x0044,

        XLLP_CIPSS   = 0x0064,           // Pixel Substitution Status register
        XLLP_CIPBUF  = 0x0068,           // Pixel Substitution Buffer
        XLLP_CIHST   = 0x006c,           // Histogram Configuration
        XLLP_CISUM   = 0x0070,           // Histogram Summation register
        XLLP_CICCR   = 0x0074,           // Compander Configuration
        XLLP_CISSC   = 0x007c,           // Spatial Scaling Configuration
        XLLP_CICMR   = 0x0090,           // Color Management Register
        XLLP_CICMC0  = 0x0094,           // Color Management Coefficients 0
        XLLP_CICMC1  = 0x0098,           // Color Management Coefficients 1
        XLLP_CICMC2  = 0x009c,           // Color Management Coefficients 2
        
        XLLP_CIFR0   = 0x00b0,           // FIFO Control Register 0
        XLLP_CIFR1   = 0x00b4,           // FIFO Control Register 1

        XLLP_CIFSR   = 0x00c0,           // FIFO Status Register

        XLLP_CIDCSR0 = 0x0200,           // DMA Controller/Status Channel 0 Register
        XLLP_CIDCSR1 = 0x0204,           // DMA Controller/Status Channel 1 Register
        XLLP_CIDCSR2 = 0x0208,           // DMA Controller/Status Channel 2 Register
        XLLP_CIDCSR3 = 0x020c,           // DMA Controller/Status Channel 3 Register
        
        XLLP_CIDBR0  = 0x0220,           // DMA Branch Channel 0 Register
        XLLP_CIDBR1  = 0x0224,           // DMA Branch Channel 1 Register
        XLLP_CIDBR2  = 0x0228,           // DMA Branch Channel 2 Register
        XLLP_CIDBR3  = 0x022c,           // DMA Branch Channel 3 Register
        
        XLLP_CIDADR0 = 0x0240,           // DMA Descriptor Address Channel 0 Register
        XLLP_CITADR0 = 0x0244,           // DMA Target Address Channel 0 Register
        XLLP_CISADR0 = 0x0248,           // DMA Source Address Channel 0 Register
        XLLP_CICMD0  = 0x024c,           // DMA Command Channel 0 Register
        
        XLLP_CIDADR1 = 0x0250,           // DMA Descriptor Address Channel 1 Register
        XLLP_CITADR1 = 0x0254,           // DMA Target Address Channel 1 Register
        XLLP_CISADR1 = 0x0258,           // DMA Source Address Channel 1 Register
        XLLP_CICMD1  = 0x025c,           // DMA Command Channel 1 Register

        XLLP_CIDADR2 = 0x0260,           // DMA Descriptor Address Channel 2 Register
        XLLP_CITADR2 = 0x0264,           // DMA Target Address Channel 2 Register
        XLLP_CISADR2 = 0x0268,           // DMA Source Address Channel 2 Register
        XLLP_CICMD2  = 0x026c,           // DMA Command Channel 2 Register

        XLLP_CIDADR3 = 0x0270,           // DMA Descriptor Address Channel 3 Register
        XLLP_CITADR3 = 0x0274,           // DMA Target Address Channel 3 Register
        XLLP_CISADR3 = 0x0278,           // DMA Source Address Channel 3 Register
        XLLP_CICMD3  = 0x027c,           // DMA Command Channel 3 Register 
};

enum XLLP_CI_REGBITS_CICR0 {
        XLLP_CI_CICR0_FOM       = ( 1UL << 0 ),
        XLLP_CI_CICR0_EOFM      = ( 1UL << 1 ),
        XLLP_CI_CICR0_SOFM      = ( 1UL << 2 ),
        XLLP_CI_CICR0_CDM       = ( 1UL << 3 ), 
        XLLP_CI_CICR0_QDM       = ( 1UL << 4 ), 
        XLLP_CI_CICR0_PERRM     = ( 1UL << 5 ),
        XLLP_CI_CICR0_EOLM      = ( 1UL << 6 ), 
        XLLP_CI_CICR0_FEM       = ( 1UL << 7 ),
        XLLP_CI_CICR0_TOM       = ( 1UL << 9 ),
        XLLP_CI_CICR0_FUM       = ( 1UL << 10 ),
        XLLP_CI_CICR0_BSM       = ( 1UL << 11 ),
        XLLP_CI_CICR0_EOFXM     = ( 1UL << 12 ),
        XLLP_CI_CICR0_GCU_EN    = ( 1UL << 21 ),
        
        XLLP_CI_CICR0_LCD_MODE_SHIFT    = 22,
        XLLP_CI_CICR0_LCD_MODE_SMASK    = 0x3,
        XLLP_CI_CICR0_LCD_MODE_DISABLED = 0x0,
        XLLP_CI_CICR0_LCD_MODE_BASE     = 0x1,
        XLLP_CI_CICR0_LCD_MODE_OVERLAY1 = 0x2,
        XLLP_CI_CICR0_LCD_MODE_OVERLAY2 = 0x3,
        
        XLLP_CI_CICR0_SIM_SHIFT = 24,
        XLLP_CI_CICR0_SIM_SMASK = 0x7,
        XLLP_CI_CICR0_DIS       = ( 1UL << 27 ),
        XLLP_CI_CICR0_ENB       = ( 1UL << 28 ),
        XLLP_CI_CICR0_SL_CAP_EN = ( 1UL << 29 ),
        XLLP_CI_CICR0_PAR_EN    = ( 1UL << 30 ),
        XLLP_CI_CICR0_INTERRUPT_MASK = ( XLLP_CI_CICR0_FOM |
                                         XLLP_CI_CICR0_EOFM |
                                         XLLP_CI_CICR0_SOFM |
                                         XLLP_CI_CICR0_CDM |
                                         XLLP_CI_CICR0_QDM |
                                         XLLP_CI_CICR0_PERRM |
                                         XLLP_CI_CICR0_EOLM |
                                         XLLP_CI_CICR0_FEM |
                                         XLLP_CI_CICR0_TOM |
                                         XLLP_CI_CICR0_FUM |
                                         XLLP_CI_CICR0_BSM |
                                         XLLP_CI_CICR0_EOFXM )
};

enum XLLP_CI_REGBITS_CICR1 {
        XLLP_CI_CICR1_DW_SHIFT       = 0,
        XLLP_CI_CICR1_DW_SMASK       = 0x7,
        XLLP_CI_CICR1_COLOR_SP_SHIFT = 3,
        XLLP_CI_CICR1_COLOR_SP_SMASK = 0x3,
        XLLP_CI_CICR1_RAW_BPP_SHIFT  = 5,
        XLLP_CI_CICR1_RAW_BPP_SMASK  = 0x3,
        XLLP_CI_CICR1_RGB_BPP_SHIFT  = 7,
        XLLP_CI_CICR1_RGB_BPP_SMASK  = 0x7,
        XLLP_CI_CICR1_YCBCR_F        = ( 1UL << 10 ),
        XLLP_CI_CICR1_RBG_F          = ( 1UL << 11 ),
        XLLP_CI_CICR1_RGB_CONV_SHIFT = 12,
        XLLP_CI_CICR1_RGB_CONV_SMASK = 0x7,
        XLLP_CI_CICR1_PPL_SHIFT      = 15,
        XLLP_CI_CICR1_PPL_SMASK      = 0xFFF,
        XLLP_CI_CICR1_RESERVED       = 0x1C000000,
        XLLP_CI_CICR1_RGBT_CONV_SHIFT= 29,
        XLLP_CI_CICR1_RGBT_CONV_SMASK= 0x3,
        XLLP_CI_CICR1_TBIT           = ( 1UL << 31 )
};

enum XLLP_CI_REGBITS_CICR2 {
        XLLP_CI_CICR2_FSW_SHIFT = 0,
        XLLP_CI_CICR2_FSW_SMASK = 0x3,
        XLLP_CI_CICR2_BFPW_SHIFT= 3,
        XLLP_CI_CICR2_BFPW_SMASK= 0x3F,
        XLLP_CI_CICR2_RESERVED  = 0x00000200,
        XLLP_CI_CICR2_HSW_SHIFT = 10,
        XLLP_CI_CICR2_HSW_SMASK = 0x3F,
        XLLP_CI_CICR2_ELW_SHIFT = 16,
        XLLP_CI_CICR2_ELW_SMASK = 0xFF,
        XLLP_CI_CICR2_BLW_SHIFT = 24,     
        XLLP_CI_CICR2_BLW_SMASK = 0xFF    
};

enum XLLP_CI_REGBITS_CICR3 {
    XLLP_CI_CICR3_LPF_SHIFT = 0,
    XLLP_CI_CICR3_LPF_SMASK = 0x7FF,
    XLLP_CI_CICR3_VSW_SHIFT = 11,
    XLLP_CI_CICR3_VSW_SMASK = 0x1F,
    XLLP_CI_CICR3_EFW_SHIFT = 16,
    XLLP_CI_CICR3_EFW_SMASK = 0xFF,
    XLLP_CI_CICR3_BFW_SHIFT = 24,
    XLLP_CI_CICR3_BFW_SMASK = 0xFF
};

enum XLLP_CI_REGBITS_CICR4 {
    XLLP_CI_CICR4_DIV_SHIFT = 0,
    XLLP_CI_CICR4_DIV_SMASK = 0xFF,
    XLLP_CI_CICR4_FR_RATE_SHIFT = 8,
    XLLP_CI_CICR4_FR_RATE_SMASK = 0x7,
    XLLP_CI_CICR4_RESERVED1 = 0x0007F800,
    XLLP_CI_CICR4_MCLK_EN   = ( 1UL << 19 ),
    XLLP_CI_CICR4_VSP       = ( 1UL << 20 ),
    XLLP_CI_CICR4_HSP       = ( 1UL << 21 ),
    XLLP_CI_CICR4_PCP       = ( 1UL << 22 ),
    XLLP_CI_CICR4_PCLK_EN   = ( 1UL << 23 ),
    XLLP_CI_CICR4_RESERVED2 = 0xFF000000,
    XLLP_CI_CICR4_RESERVED  = XLLP_CI_CICR4_RESERVED1 | XLLP_CI_CICR4_RESERVED2
};

enum XLLP_CI_REGBITS_CISR {
    XLLP_CI_CISR_EOF        = ( 1UL << 3 ),
    XLLP_CI_CISR_SOF        = ( 1UL << 4 ),
    XLLP_CI_CISR_CDD        = ( 1UL << 5 ),
    XLLP_CI_CISR_CQD        = ( 1UL << 6 ),
    XLLP_CI_CISR_PAR_ERR    = ( 1UL << 7 ),
    XLLP_CI_CISR_EOL        = ( 1UL << 8 ),
    XLLP_CI_CISR_HST_INT    = ( 1UL << 9 ),
    XLLP_CI_CISR_CGU_INT    = ( 1UL << 10 ),
    XLLP_CI_CISR_FTO        = ( 1UL << 15 ),
    XLLP_CI_CISR_EOFX       = ( 1UL << 30 ),
    XLLP_CI_CISR_SINT       = ( 1UL << 31 ),
    XLLP_CI_CISR_MASK       = ( XLLP_CI_CISR_EOF |
                                XLLP_CI_CISR_SOF |
                                XLLP_CI_CISR_CDD |
                                XLLP_CI_CISR_CQD |
                                XLLP_CI_CISR_PAR_ERR |
                                XLLP_CI_CISR_EOL |
                                //XLLP_CI_CISR_HST_INT |
                                XLLP_CI_CISR_CGU_INT |
                                XLLP_CI_CISR_FTO |
                                XLLP_CI_CISR_EOFX |
                                XLLP_CI_CISR_SINT)
};

enum XLLP_CI_REGBITS_CIFSR {
    XLLP_CI_CIFSR_IFO_0        = ( 1UL << 0  ),
    XLLP_CI_CIFSR_IFO_1        = ( 1UL << 1  ),
    XLLP_CI_CIFSR_IFO_2        = ( 1UL << 2  ),
    XLLP_CI_CIFSR_IFO_3        = ( 1UL << 3  ),
    XLLP_CI_CIFSR_EOF3         = ( 1UL << 10 ),
    XLLP_CI_CIFSR_SOF0         = ( 1UL << 14 ),
    XLLP_CI_CIFSR_SOF1         = ( 1UL << 15 ),
    XLLP_CI_CIFSR_SOF2         = ( 1UL << 16 ),
    XLLP_CI_CIFSR_SOF3         = ( 1UL << 17 ),
    XLLP_CI_CIFSR_BS0          = ( 1UL << 21 ),
    XLLP_CI_CIFSR_BS1          = ( 1UL << 22 ),
    XLLP_CI_CIFSR_BS2          = ( 1UL << 23 ),
    XLLP_CI_CIFSR_BS3          = ( 1UL << 24 ),
    XLLP_CI_CIFSR_IFU_3        = ( 1UL << 28 ),
};

enum XLLP_CI_REGBITS_CIPSS {
    XLLP_CI_CIPSS_PXLCNT_SHIFT  = 0,
    XLLP_CI_CIPSS_PXLCNT_SMASK  = 0xFFF,
    
    XLLP_CI_CIPSS_LNCNT_SHIFT   = 12,
    XLLP_CI_CIPSS_LNCNT_SMASK   = 0xFFF,
    
    XLLP_CI_CIPSS_RAMADDR_SHIFT = 24,
    XLLP_CI_CIPSS_RAMADDR_SMASK = 0x7F,
    
    XLLP_CI_CIPSS_PSU_EN        = ( 1UL << 31)
};

enum XLLP_CI_REGBITS_CIPBUF {
    XLLP_CI_CIPBUF_DEADROW_SHIFT = 0,
    XLLP_CI_CIPBUF_DEADROW_SMASK = 0xFFF,    
    XLLP_CI_CIPBUF_DEADCOL_SHIFT = 16,
    XLLP_CI_CIPBUF_DEADCOL_SMASK = 0xFFF,
};

enum XLLP_CI_REGBITS_CIHST {
    XLLP_CI_CIHST_COLOR_SEL_SHIFT = 0,
    XLLP_CI_CIHST_COLOR_SEL_SMASK = 0xF,
    XLLP_CI_CIHST_COLOR_RED       = 0x1,
    XLLP_CI_CIHST_COLOR_BLUE      = 0x2,
    XLLP_CI_CIHST_COLOR_GREEN1    = 0x4,
    XLLP_CI_CIHST_COLOR_GREEN2    = 0x8,
    
    XLLP_CI_CIHST_SCALE_SHIFT     = 4,
    XLLP_CI_CIHST_SCALE_SMASK     = 0x3,
    XLLP_CI_CIHST_SCALE_0_TO_7    = 0x0,
    XLLP_CI_CIHST_SCALE_0_TO_8    = 0x1,
    XLLP_CI_CIHST_SCALE_1_TO_9    = 0x2,
    
    XLLP_CI_CIHST_CLR_RAM         = ( 1UL << 6 )
};


enum XLLP_CI_REGBITS_CICCR {
    XLLP_CI_CICCR_EN         = ( 1UL << 0 ),
        
    XLLP_CI_CICCR_SCALE_SHIFT  = 1,
    XLLP_CI_CICCR_SCALE_SMASK  = 0x3,
    XLLP_CI_CICCR_SCALE_0_TO_7 = 0x0,
    XLLP_CI_CICCR_SCALE_1_TO_8 = 0x1,
    XLLP_CI_CICCR_SCALE_2_TO_9 = 0x2,
    
    XLLP_CI_CICCR_CLUT_SHIFT = 3,
    XLLP_CI_CICCR_CLUT_SMASK = 0xFF,
    XLLP_CI_CICCR_CLUT_RED   = 0x00,
    XLLP_CI_CICCR_CLUT_BLUE  = 0x20,
    XLLP_CI_CICCR_CLUT_GREEN = 0x40,
    
    XLLP_CI_CICCR_BLC_SHIFT  = 11,
    XLLP_CI_CICCR_BLC_SMASK  = 0xFF,
    
    XLLP_CI_CICCR_LUT_LD     = ( 1UL << 19)
};

enum XLLP_CI_REGBITS_CISSC {
    XLLP_CI_CISSC_SCALE_SHIFT   = 0,
    XLLP_CI_CISSC_SCALE_SMASK   = 0x3,
    XLLP_CI_CISSC_SCALE_DISABLE = 0x0,
    XLLP_CI_CISSC_SCALE_2_TO_1  = 0x1,
    XLLP_CI_CISSC_SCALE_4_TO_1  = 0x2
};

enum XLLP_CI_REGBITS_CICMR {
    XLLP_CI_CICMR_DMODE_SHIFT   = 0,
    XLLP_CI_CICMR_DMODE_SMASK   = 0x3,
    XLLP_CI_CICMR_DMODE_DISABLE = 0x0,
    XLLP_CI_CICMR_DMODE_RGB     = 0x1,
    XLLP_CI_CICMR_DMODE_YUV     = 0x2
};

enum XLLP_CI_REGBITS_CICMC0 {
    XLLP_CI_CICMC0_COF02_SHIFT = 0,
    XLLP_CI_CICMC0_COF02_SMASK = 0x3FF,
    
    XLLP_CI_CICMC0_COF01_SHIFT = 10,
    XLLP_CI_CICMC0_COF01_SMASK = 0x3FF,

    XLLP_CI_CICMC0_COF00_SHIFT = 20,
    XLLP_CI_CICMC0_COF00_SMASK = 0x3FF,
};

enum XLLP_CI_REGBITS_CICMC1 {
    XLLP_CI_CICMC1_COF12_SHIFT = 0,
    XLLP_CI_CICMC1_COF12_SMASK = 0x3FF,
    
    XLLP_CI_CICMC1_COF11_SHIFT = 10,
    XLLP_CI_CICMC1_COF11_SMASK = 0x3FF,

    XLLP_CI_CICMC1_COF10_SHIFT = 20,
    XLLP_CI_CICMC1_COF10_SMASK = 0x3FF,
};

enum XLLP_CI_REGBITS_CICMC2 {
    XLLP_CI_CICMC2_COF22_SHIFT = 0,
    XLLP_CI_CICMC2_COF22_SMASK = 0x3FF,
    
    XLLP_CI_CICMC2_COF21_SHIFT = 10,
    XLLP_CI_CICMC2_COF21_SMASK = 0x3FF,

    XLLP_CI_CICMC2_COF20_SHIFT = 20,
    XLLP_CI_CICMC2_COF20_SMASK = 0x3FF,
};


enum XLLP_CI_REGBITS_CIFR0 {
    XLLP_CI_CIFR_FEN0       = ( 1UL << 0 ),
    XLLP_CI_CIFR_FEN1       = ( 1UL << 1 ),
    XLLP_CI_CIFR_FEN2       = ( 1UL << 2 ),
    XLLP_CI_CIFR_RESETF     = ( 1UL << 3 ),
    
    XLLP_CI_CIFR_THL_0_SHIFT= 4,
    XLLP_CI_CIFR_THL_0_SMASK= 0x3,
    
    XLLP_CI_CIFR_RESERVED1  = 0x000000C0,
    
    XLLP_CI_CIFR_FLVL0_SHIFT= 8,
    XLLP_CI_CIFR_FLVL0_SMASK= 0xFF,
    
    XLLP_CI_CIFR_FLVL1_SHIFT= 16,
    XLLP_CI_CIFR_FLVL1_SMASK= 0x7F,
    
    XLLP_CI_CIFR_FLVL2_SHIFT= 23,
    XLLP_CI_CIFR_FLVL2_SMASK= 0x7F,
    
    XLLP_CI_CIFR_RESERVED2  = 0xC0000000,
    XLLP_CI_CIFR_RESERVED   = XLLP_CI_CIFR_RESERVED1 | XLLP_CI_CIFR_RESERVED2 
};

enum XLLP_CI_REGBITS_CIFR1  {
    XLLP_CI_CIFR_FEN3       = ( 1UL << 0 ),
        
    XLLP_CI_CIFR_FLVL3_SHIFT= 1,
    XLLP_CI_CIFR_FLVL3_SMASK= 0xFF,
};

enum XLLP_CI_REGBITS_CIDBR {
    XLLP_CI_CIDBR_BRA           = ( 1UL << 0 ),
    XLLP_CI_CIDBR_BINT          = ( 1UL << 1 ),
    XLLP_CI_CIDBR_SRCADDR_SMASK = 0xFFFFFFF0,
};

//---------------------------------------------------------------------------
//     Parameter Type definitions
//---------------------------------------------------------------------------
typedef enum  {
        XLLP_CI_RAW8 = 0,                   //RAW
        XLLP_CI_RAW9,
        XLLP_CI_RAW10,
        XLLP_CI_YCBCR422,               //YCBCR
        XLLP_CI_YCBCR422_PLANAR,        //YCBCR Planaried
        XLLP_CI_RGB444,                 //RGB
        XLLP_CI_RGB555,
        XLLP_CI_RGB565,
        XLLP_CI_RGB666,
        XLLP_CI_RGB888,
        XLLP_CI_RGBT555_0,              //RGB+Transparent bit 0
        XLLP_CI_RGBT888_0,
        XLLP_CI_RGBT555_1,              //RGB+Transparent bit 1  
        XLLP_CI_RGBT888_1,
        XLLP_CI_RGB666_PACKED,          //RGB Packed 
        XLLP_CI_RGB888_PACKED,
        XLLP_CI_INVALID_FORMAT = 0xFF
} XLLP_CI_IMAGE_FORMAT;

// Interrupt mask
typedef enum {
    XLLP_CI_INT_IFO              = ( 1UL << 0 ),   // FIFO Overrun Mask
    XLLP_CI_INT_EOF              = ( 1UL << 1 ),   // Quick Capture Interface End-of-Frame Mask
    XLLP_CI_INT_SOF              = ( 1UL << 2 ),   // Quick Capture Interface Start-of-Frame Mask   
    XLLP_CI_INT_CDD              = ( 1UL << 3 ),   // Quick Capture Interface Disable Done Mask
    XLLP_CI_INT_CQD              = ( 1UL << 4 ),   // Quick Capture Interface Quick Disable Mask
    XLLP_CI_INT_PAR_ERR          = ( 1UL << 5 ),   // Parity Error Mask
    XLLP_CI_INT_EOL              = ( 1UL << 6 ),   // End-of-Line Mask
    XLLP_CI_INT_FEMPTY           = ( 1UL << 7 ),   // FIFO Empty Mask
    XLLP_CI_INT_FTO              = ( 1UL << 9 ),   // Time-Out Mask
    XLLP_CI_INT_FU               = ( 1UL << 10 ),  // Input FIFO Underrun Mask Channel 3
    XLLP_CI_INT_BS               = ( 1UL << 11 ),  // Branch Status Mask
    XLLP_CI_INT_EOFX             = ( 1UL << 12 ),  // End-of-Frame Transfer to Memory Mask
    XLLP_CI_INT_SC0              = ( 1UL << 13 ),  // Stop Channel Interrupt Mask - Channel 0
    XLLP_CI_INT_SC1              = ( 1UL << 14 ),  // Stop Channel Interrupt Mask - Channel 1
    XLLP_CI_INT_SC2              = ( 1UL << 15 ),  // Stop Channel Interrupt Mask - Channel 2
    XLLP_CI_INT_SC3              = ( 1UL << 16 )   // Stop Channel Interrupt Mask - Channel 3
} XLLP_CI_INTERRUPT_MASK;

#define XLLP_CICR0_VAL(ci_int_mask) \
    ((ci_int_mask) & XLLP_CI_CICR0_INTERRUPT_MASK )                        
    
#define XLLP_CIDCSR0_VAL(ci_int_mask) \
    (((!((ci_int_mask) & (1UL << 13))) >> 13) << 29)     // convert XLLP_CI_INT_SC0 to CIDCSR0[StopIrqEn]
    
#define XLLP_CIDCSR1_VAL(ci_int_mask) \
    (((!((ci_int_mask) & (1UL << 14))) >> 14) << 29)     // convert XLLP_CI_INT_SC1 to CIDCSR1[StopIrqEn]                          
    
#define XLLP_CIDCSR2_VAL(ci_int_mask) \
    (((!((ci_int_mask) & (1UL << 15))) >> 15) << 29)     // convert XLLP_CI_INT_SC2 to CIDCSR2[StopIrqEn]
    
#define XLLP_CIDCSR3_VAL(ci_int_mask) \
    (((!((ci_int_mask) & (1UL << 16))) >> 16) << 29)     // convert XLLP_CI_INT_SC3 to CIDCSR3[StopIrqEn]

#define XLLP_CI_INT_MASK(cicr0_val, cidcsr0_val, cidcsr1_val, cidcsr2_val, cidcsr3_val) \
    (((cicr0_val) & XLLP_CI_CICR0_INTERRUPT_MASK) | \
    ((!((cidcsr0_val) & (1UL << 29))) << 13) | \
    ((!((cidcsr1_val) & (1UL << 29))) << 14) | \
    ((!((cidcsr2_val) & (1UL << 29))) << 15) | \
    ((!((cidcsr3_val) & (1UL << 29))) << 16)   \
    )

/*
notes:

mapping between ci_int_mask and related registers bits:
ci_int_mask:
 -----------------------------------------------------------------------------------------------
|  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |
|31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10| 9| 8| 7| 6| 5| 4| 3| 2| 1| 0|
|  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |
 -----------------------------------------------------------------------------------------------
 |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  | 
 |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  | 
 |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |--- CICR0[FOM]
 |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |------ CICR0[EOFM]  
 |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |--------- CICR0[SOFM]
 |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |------------ CICR0[CDM]
 |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |--------------- CICR0[QDM]
 |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |------------------ CICR0[PERRM]
 |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |--------------------- CICR0[EOLM]
 |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |------------------------ CICR0[FEM]
 |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |--------------------------- N/A
 |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |------------------------------ CICR0[TOM]
 |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |--------------------------------- CICR0[FUM]
 |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |------------------------------------ CICR0[BSM]
 |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |--------------------------------------- CICR0[EOFM]
 |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |------------------------------------------ CIDCSR0[StopIrqEn]
 |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |--------------------------------------------- CIDCSR1[StopIrqEn]
 |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |------------------------------------------------ CIDCSR2[StopIrqEn]
 |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |--------------------------------------------------- CIDCSR3[StopIrqEn]
 |  |  |  |  |  |  |  |  |  |  |  |  |  |  |------------------------------------------------------ N/A
 |  |  |  |  |  |  |  |  |  |  |  |  |  |--------------------------------------------------------- N/A
 |  |  |  |  |  |  |  |  |  |  |  |  |------------------------------------------------------------ N/A
 |  |  |  |  |  |  |  |  |  |  |  |--------------------------------------------------------------- N/A
 |  |  |  |  |  |  |  |  |  |  |------------------------------------------------------------------ N/A
 |  |  |  |  |  |  |  |  |  |--------------------------------------------------------------------- N/A
 |  |  |  |  |  |  |  |  |------------------------------------------------------------------------ N/A
 |  |  |  |  |  |  |  |--------------------------------------------------------------------------- N/A
 |  |  |  |  |  |  |------------------------------------------------------------------------------ N/A
 |  |  |  |  |  |--------------------------------------------------------------------------------- N/A
 |  |  |  |  |------------------------------------------------------------------------------------ N/A
 |  |  |  |--------------------------------------------------------------------------------------- N/A
 |  |  |------------------------------------------------------------------------------------------ N/A
 |  |--------------------------------------------------------------------------------------------- N/A
 |------------------------------------------------------------------------------------------------ N/A


#define XLLP_CI_INT_MASK(cicr0_val, cidcsr0_val, cidcsr1_val, cidcsr2_val, cidcsr3_val) \
    (((cicr0_val) & XLLP_CI_CICR0_INTERRUPT_MASK) | \   // merge CICR0[FOM, ..., EOFXM]
     ((!((cidcsr0_val) & (1UL << 29))) << 13) | \        // merge CIDCSR0[StopIrqEn]
     ((!((cidcsr1_val) & (1UL << 29))) << 14) | \        // merge CIDCSR1[StopIrqEn]
     ((!((cidcsr2_val) & (1UL << 29))) << 15) | \        // merge CIDCSR2[StopIrqEn]
     ((!((cidcsr3_val) & (1UL << 29))) << 16)   \        // merge CIDCSR3[StopIrqEn]
     )
*/

// Interrupt status   
typedef enum {
    XLLP_CI_INTSTATUS_EOF3            = ( 1UL << 0  ),  // End-of-Frame for Channel 3, depending on Channel 0 DMA channel descriptor Chain configuration
    XLLP_CI_INTSTATUS_FU_3            = ( 1UL << 1  ),  // FIFO Underrun for Channel 3, masked by XLLP_CI_INT_FU
    XLLP_CI_INTSTATUS_EOF             = ( 1UL << 3  ),  // End-of-Frame, masked by XLLP_CI_INT_EOF
    XLLP_CI_INTSTATUS_SOF             = ( 1UL << 4  ),  // Start-of-Frame, masked by XLLP_CI_INT_SOF
    XLLP_CI_INTSTATUS_CDD             = ( 1UL << 5  ),  // Quick Capture Interface Disable Done, masked by XLLP_CI_INT_CDD
    XLLP_CI_INTSTATUS_CQD             = ( 1UL << 6  ),  // Quick Capture Interface Quick Disable Status, masked by XLLP_CI_INT_CQD .
    XLLP_CI_INTSTATUS_PAR_ERR         = ( 1UL << 7  ),  // Parity Error, masked by XLLP_CI_INT_PAR_ERR
    XLLP_CI_INTSTATUS_EOL             = ( 1UL << 8  ),  // End of Line, masked by XLLP_CI_INT_EOL
    XLLP_CI_INTSTATUS_HST_INT         = ( 1UL << 9  ),  // Histogram Interrupt, unmaskable
    XLLP_CI_INTSTATUS_CGC_INT         = ( 1UL << 10 ),  // Compander Interrupt, unmaskable
    XLLP_CI_INTSTATUS_IFO_0           = ( 1UL << 11 ),  // FIFO Overrun for Channel 0, masked by XLLP_CI_INT_IFO
    XLLP_CI_INTSTATUS_IFO_1           = ( 1UL << 12 ),  // FIFO Overrun for Channel 1, masked by XLLP_CI_INT_IFO
    XLLP_CI_INTSTATUS_IFO_2           = ( 1UL << 13 ),  // FIFO Overrun for Channel 2, masked by XLLP_CI_INT_IFO
    XLLP_CI_INTSTATUS_IFO_3           = ( 1UL << 14 ),  // FIFO Overrun for Channel 3, masked by XLLP_CI_INT_IFO
    XLLP_CI_INTSTATUS_FTO             = ( 1UL << 15 ),  // FIFO Time-out, masked by XLLP_CI_INT_FTO
    XLLP_CI_INTSTATUS_BS0             = ( 1UL << 16 ),  // Branch Status for Channel 0, masked by XLLP_CI_INT_BS
    XLLP_CI_INTSTATUS_BS1             = ( 1UL << 17 ),  // Branch Status for Channel 1, masked by XLLP_CI_INT_BS
    XLLP_CI_INTSTATUS_BS2             = ( 1UL << 18 ),  // Branch Status for Channel 2, masked by XLLP_CI_INT_BS
    XLLP_CI_INTSTATUS_BS3             = ( 1UL << 19 ),  // Branch Status for Channel 3, masked by XLLP_CI_INT_BS
    XLLP_CI_INTSTATUS_SOF0            = ( 1UL << 20 ),  // Start-of-Frame for Channel 0, depending on Channel 0 DMA channel descriptor Chain configuration
    XLLP_CI_INTSTATUS_SOF1            = ( 1UL << 21 ),  // Start-of-Frame for Channel 1, depending on Channel 1 DMA channel descriptor Chain configuration
    XLLP_CI_INTSTATUS_SOF2            = ( 1UL << 22 ),  // Start-of-Frame for Channel 2, depending on Channel 2 DMA channel descriptor Chain configuration
    XLLP_CI_INTSTATUS_SOF3            = ( 1UL << 23 ),  // Start-of-Frame for Channel 3, depending on Channel 3 DMA channel descriptor Chain configuration
    XLLP_CI_INTSTATUS_SC0             = ( 1UL << 24 ),  // Stop interrupt Channel 0, masked by XLLP_CI_INT_SC0
    XLLP_CI_INTSTATUS_SC1             = ( 1UL << 25 ),  // Stop interrupt Channel 1, masked by XLLP_CI_INT_SC1
    XLLP_CI_INTSTATUS_SC2             = ( 1UL << 26 ),  // Stop interrupt Channel 2, masked by XLLP_CI_INT_SC2
    XLLP_CI_INTSTATUS_SC3             = ( 1UL << 27 ),  // Stop interrupt Channel 3, masked by XLLP_CI_INT_SC3
	XLLP_CI_INTSTATUS_BUSERR          = ( 1UL << 28 ),  // Bus error in One or more DMA channels.
    XLLP_CI_INTSTATUS_SINT            = ( 1UL << 31 ),  // Subsequent Interrupt Status, unmaskable
    XLLP_CI_INTSTATUS_EOFX            = ( 1UL << 30 )   // End-of-Frame Transferred to Memory (Channel 0-2, not Channel 3), masked by XLLP_CI_INT_EOFX
} XLLP_CI_INTERRUPT_STATUS;

#define XLLP_CISR_VAL(ci_int_status) \
    ((ci_int_status) & XLLP_CI_CISR_MASK)

#define XLLP_CIFSR_VAL(ci_int_status) \
    ( \
    ((((ci_int_status) & (0xf << 11)) >> 11) << 0  ) | \
    ((((ci_int_status) & (0x1 << 1 )) >>  1) << 28 ) | \
    ((((ci_int_status) & (0xf << 16)) >> 16) << 21 ) | \
    ((((ci_int_status) & (0x1 << 0 )) >> 0 ) << 10 ) | \
    ((((ci_int_status) & (0xf << 20)) >> 20) << 14 )   \
    )

#define XLLP_CIDCSR0_STATUS_VAL(ci_int_status) \
    ((((ci_int_status) & (0x1 << 24)) >> 24) << 3  )

#define XLLP_CIDCSR1_STATUS_VAL(ci_int_status) \
    ((((ci_int_status) & (0x1 << 25)) >> 25) << 3  )

#define XLLP_CIDCSR2_STATUS_VAL(ci_int_status) \
    ((((ci_int_status) & (0x1 << 26)) >> 26) << 3  )

#define XLLP_CIDCSR3_STATUS_VAL(ci_int_status) \
    ((((ci_int_status) & (0x1 << 27)) >> 27) << 3  )

#define XLLP_CI_INT_STATUS(cisr_val, cifsr_val, cidcsr0_val, cidcsr1_val, cidcsr2_val, cidcsr3_val) \
    (((cisr_val) & XLLP_CI_CISR_MASK) | \
     ((((cifsr_val) & (0xf << 0 ) ) >> 0  ) << 11 ) | \
     ((((cifsr_val) & (0x1 << 10) ) >> 10 ) << 0  ) | \
     ((((cifsr_val) & (0xf << 14) ) >> 14 ) << 20 ) | \
     ((((cifsr_val) & (0xf << 21) ) >> 21 ) << 16 ) | \
     ((((cifsr_val) & (0x1 << 28) ) >> 28 ) << 1  ) | \
     ((((cidcsr0_val) & (0x1 << 3)) >> 3  ) << 24 ) | \
     ((((cidcsr1_val) & (0x1 << 3)) >> 3  ) << 25 ) | \
     ((((cidcsr2_val) & (0x1 << 3)) >> 3  ) << 26 ) | \
     ((((cidcsr3_val) & (0x1 << 3)) >> 3  ) << 27 ) | \
     ((((cidcsr0_val) & (0x1 << 0)) >> 0  ) << 28 ) | \
     ((((cidcsr1_val) & (0x1 << 0)) >> 0  ) << 28 ) | \
     ((((cidcsr2_val) & (0x1 << 0)) >> 0  ) << 28 ) | \
     ((((cidcsr3_val) & (0x1 << 0)) >> 0  ) << 28 )   \
     )

/*
note:

mapping between ci_int_status and related registers bits:
ci_int_status:
 -----------------------------------------------------------------------------------------------
|  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |
|31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10| 9| 8| 7| 6| 5| 4| 3| 2| 1| 0|
|  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |
 -----------------------------------------------------------------------------------------------
 |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  | 
 |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  | 
 |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |--- CIFSR[EOF3]
 |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |------ CIFSR[FU_3]  
 |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |--------- N/A
 |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |------------ CISR[EOF]
 |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |--------------- CISR[SOF]
 |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |------------------ CISR[CDD]
 |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |--------------------- CISR[CQD]
 |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |------------------------ CISR[PAR_ERR]
 |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |--------------------------- CISR[EOL]
 |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |------------------------------ CISR[HST_INT]
 |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |--------------------------------- CISR[CGC_INT]
 |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |------------------------------------ CIFSR[IFO_0]
 |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |--------------------------------------- CIFSR[IFO_1]
 |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |------------------------------------------ CIFSR[IFO_2]
 |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |--------------------------------------------- CIFSR[IFO_3]
 |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |------------------------------------------------ CISR[FTO]
 |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |--------------------------------------------------- CIFSR[BS0]
 |  |  |  |  |  |  |  |  |  |  |  |  |  |  |------------------------------------------------------ CIFSR[BS1]
 |  |  |  |  |  |  |  |  |  |  |  |  |  |--------------------------------------------------------- CIFSR[BS2]
 |  |  |  |  |  |  |  |  |  |  |  |  |------------------------------------------------------------ CIFSR[BS3]
 |  |  |  |  |  |  |  |  |  |  |  |--------------------------------------------------------------- CIFSR[SOF0]
 |  |  |  |  |  |  |  |  |  |  |------------------------------------------------------------------ CIFSR[SOF1]
 |  |  |  |  |  |  |  |  |  |--------------------------------------------------------------------- CIFSR[SOF2]
 |  |  |  |  |  |  |  |  |------------------------------------------------------------------------ CIFSR[SOF3]
 |  |  |  |  |  |  |  |--------------------------------------------------------------------------- CIDCSR0[StopIrq]
 |  |  |  |  |  |  |------------------------------------------------------------------------------ CIDCSR1[StopIrq]
 |  |  |  |  |  |--------------------------------------------------------------------------------- CIDCSR2[StopIrq]]
 |  |  |  |  |------------------------------------------------------------------------------------ CIDCSR3[StopIrq]
 |  |  |  |--------------------------------------------------------------------------------------- CIDCSR0[BusErrIntr] | CIDCSR1[BusErrIntr] | CIDCSR2[BusErrIntr]| CIDCSR3[BusErrIntr] 
 |  |  |------------------------------------------------------------------------------------------ N/A
 |  |--------------------------------------------------------------------------------------------- CISR[EOFX]
 |------------------------------------------------------------------------------------------------ CISR[SINT]
 
#define XLLP_CIFSR_VAL(ci_int_status) \
    ( \
    ((((ci_int_status) & (0xf << 11)) >> 11) << 0  ) | \ convert XLLP_CI_INTSTATUS_IFO_0~3 to CIFSR[IFO_0~IFO_3]
    ((((ci_int_status) & (0x1 << 1 )) >>  1) << 28 ) | \ convert XLLP_CI_INTSTATUS_FU_3 to CIFSR[FU_3]
    ((((ci_int_status) & (0xf << 16)) >> 16) << 21 ) | \ convert XLLP_CI_INTSTATUS_BS0~3 to CIFSR[BS0~BS3]
    ((((ci_int_status) & (0x1 << 0 )) >> 0 ) << 10 ) | \ convert XLLP_CI_INTSTATUS_EOF3 to CIFSR[EOF3]
    ((((ci_int_status) & (0xf << 20)) >> 20) << 14 )   \ convert XLLP_CI_INTSTATUS_SOF0~3 to CIFSR[SOF0~SOF3]
    )

#define XLLP_CI_INT_STATUS(cisr_val, cifsr_val, cidcsr0_val, cidcsr1_val, cidcsr2_val, cidcsr3_val) \
    (((cisr_val) & XLLP_CI_CISR_MASK) | \                // merge CISR
     ((((cifsr_val) & (0xf << 0 ) ) >> 0  ) << 11 ) | \  // merge CIFSR[IFO_0, IFO_1, IFO_2, IFO_3]
     ((((cifsr_val) & (0x1 << 10) ) >> 10 ) << 0  ) | \  // merge CIFSR[EOF3]
     ((((cifsr_val) & (0xf << 14) ) >> 14 ) << 20 ) | \  // merge CIFSR[SOF0, SOF1, SOF2, SOF3]
     ((((cifsr_val) & (0xf << 21) ) >> 21 ) << 16 ) | \  // merge CIFSR[BS0, BS1, BS2, BS3]
     ((((cifsr_val) & (0x1 << 28) ) >> 28 ) << 1  ) | \  // merge CIFSR[FU_3]
     ((((cidcsr0_val) & (0x1 << 3)) >> 3  ) << 24 ) | \  // merge CIDCSR0[StopIrq]
     ((((cidcsr1_val) & (0x1 << 3)) >> 3  ) << 25 ) | \  // merge CIDCSR1[StopIrq]
     ((((cidcsr2_val) & (0x1 << 3)) >> 3  ) << 26 ) | \  // merge CIDCSR2[StopIrq]
     ((((cidcsr3_val) & (0x1 << 3)) >> 3  ) << 27 )   \  // merge CIDCSR3[StopIrq]
    )
*/

typedef enum XLLP_CI_MODE {
        XLLP_CI_MODE_MP,             // Master-Parallel
        XLLP_CI_MODE_SP,             // Slave-Parallel
        XLLP_CI_MODE_MS,             // Master-Serial
        XLLP_CI_MODE_EP,             // Embedded-Parallel
        XLLP_CI_MODE_ES              // Embedded-Serial
} XLLP_CI_MODE;


typedef enum  {
        XLLP_CI_FR_ALL = 0,          // Capture all incoming frames
        XLLP_CI_FR_1_2,              // Capture 1 out of every 2 frames
        XLLP_CI_FR_1_3,              // Capture 1 out of every 3 frames
        XLLP_CI_FR_1_4,
        XLLP_CI_FR_1_5,
        XLLP_CI_FR_1_6,
        XLLP_CI_FR_1_7,
        XLLP_CI_FR_1_8
} XLLP_CI_FRAME_CAPTURE_RATE;


typedef enum  {
        XLLP_CI_FIFO_THL_32 = 0,
        XLLP_CI_FIFO_THL_64,
        XLLP_CI_FIFO_THL_96
} XLLP_CI_FIFO_THRESHOLD;

typedef struct {
    unsigned int BFW;
    unsigned int BLW;
} XLLP_CI_MP_TIMING, XLLP_CI_MS_TIMING;

typedef struct {
    unsigned int BLW;
    unsigned int ELW; 
    unsigned int HSW;
    unsigned int BFPW;
    unsigned int FSW; 
    unsigned int BFW;
    unsigned int EFW;
    unsigned int VSW; 
} XLLP_CI_SP_TIMING;

typedef enum {
    XLLP_CI_DATA_WIDTH4 = 0x0,
    XLLP_CI_DATA_WIDTH5 = 0x1,
    XLLP_CI_DATA_WIDTH8 = 0x2,  
    XLLP_CI_DATA_WIDTH9 = 0x3,  
    XLLP_CI_DATA_WIDTH10= 0x4   
} XLLP_CI_DATA_WIDTH;

//-------------------------------------------------------------------------------------------------------
//      Configuration APIs
//-------------------------------------------------------------------------------------------------------
void XllpCISetFrameRate(unsigned int ci_reg_base, XLLP_CI_FRAME_CAPTURE_RATE frate);
XLLP_CI_FRAME_CAPTURE_RATE XllpCIGetFrameRate(unsigned int ci_reg_base);
void XllpCISetImageFormat(unsigned int ci_reg_base, XLLP_CI_IMAGE_FORMAT input_format, XLLP_CI_IMAGE_FORMAT output_format); 
void XllpCISetMode(unsigned int ci_reg_base, XLLP_CI_MODE mode, XLLP_CI_DATA_WIDTH data_width);
void XllpCIConfigureMP(unsigned int ci_reg_base, unsigned int PPL, unsigned int LPF, XLLP_CI_MP_TIMING* timing);
void XllpCIConfigureSP(unsigned int ci_reg_base, unsigned int PPL, unsigned int LPF, XLLP_CI_SP_TIMING* timing);
void XllpCIConfigureMS(unsigned int ci_reg_base, unsigned int PPL, unsigned int LPF, XLLP_CI_MS_TIMING* timing);
void XllpCIConfigureEP(unsigned int ci_reg_base, int parity_check);
void XllpCIConfigureES(unsigned int ci_reg_base, int parity_check);
void XllpCISetClock(unsigned int ci_reg_base, unsigned int clk_regs_base, int pclk_enable, int mclk_enable, unsigned int mclk_mhz);
void XllpCISetPolarity(unsigned int ci_reg_base, int pclk_sample_falling, int hsync_active_low, int vsync_active_low);
void XllpCISetFIFO(unsigned int ci_reg_base, unsigned int timeout, XLLP_CI_FIFO_THRESHOLD threshold, int fifo1_enable, 
                   int fifo2_enable);
void XllpCIResetFIFO(unsigned int ci_reg_base);
void XllpCISetInterruptMask(unsigned int ci_reg_base, unsigned int mask);
unsigned int XllpCIGetInterruptMask(unsigned int ci_reg_base);
void XllpCIClearInterruptStatus(unsigned int ci_reg_base, unsigned int status);
unsigned int XllpCIGetInterruptStatus(unsigned int ci_reg_base);
void XllpCISetRegisterValue(unsigned int ci_reg_base, unsigned int reg_offset, unsigned int value);
void XllpCIDisableComplete(unsigned int ci_reg_base);

//-------------------------------------------------------------------------------------------------------
//      Control APIs
//-------------------------------------------------------------------------------------------------------
void XllpCIInit(unsigned int ci_reg_base, unsigned int clk_regs_base);
void XllpCIDeInit(unsigned int ci_reg_base, unsigned int clk_regs_base);
void XllpCIEnable(unsigned int ci_reg_base/*, int dma_en*/);
int  XllpCIDisable(unsigned int ci_reg_base, unsigned int ost_reg_base, int quick, int wait_for_disable_complete );
void XllpCISlaveCaptureEnable(unsigned int ci_reg_base);
void XllpCISlaveCaptureDisable(unsigned int ci_reg_base);

//-------------------------------------------------------------------------------------------------------
//      CI RAW data processing chain APIs
//-------------------------------------------------------------------------------------------------------

// Histogram Unit(HSU) related functions
typedef enum {
    XLLP_CI_HISTO_RED     = XLLP_CI_CIHST_COLOR_RED,
    XLLP_CI_HISTO_BLUE    = XLLP_CI_CIHST_COLOR_BLUE,
    XLLP_CI_HISTO_GREEN1  = XLLP_CI_CIHST_COLOR_GREEN1,
    XLLP_CI_HISTO_GREEN2  = XLLP_CI_CIHST_COLOR_GREEN2
} XLLP_CI_HSU_COLOR_TYPE;

typedef enum {
    XLLP_CI_HSU_MUX_0_TO_7  = XLLP_CI_CIHST_SCALE_0_TO_7,    // for 8bit raw data
    XLLP_CI_HSU_MUX_0_TO_8  = XLLP_CI_CIHST_SCALE_0_TO_8,    // for 9bit raw data
    XLLP_CI_HSU_MUX_1_TO_9  = XLLP_CI_CIHST_SCALE_1_TO_9     // for 10bit raw data
} XLLP_CI_HSU_MUX_SEL_TYPE;

XLLP_STATUS_T XllpCIHSUGetHistgram (
                            unsigned int  ci_reg_base,
                            unsigned int  ost_reg_base, 
                  XLLP_CI_HSU_COLOR_TYPE  color_type,
                 XLLP_CI_HSU_MUX_SEL_TYPE mux_select,
                            unsigned int *histogram_lut_buffer_virtual, 
                            unsigned int  histogram_lut_buffer_physical , 
                            unsigned int *histogram_lut_dma_descriptors_virtual, 
                            unsigned int  histogram_lut_dma_descriptors_physical, 
                            unsigned int  histogram_size,
                            unsigned int *histogram_sum);

// Pixel Substitute(PSU) related functions
XLLP_STATUS_T XllpCIPSUTagBadPixelAt(unsigned int ci_reg_base, int column, int row);

XLLP_STATUS_T XllpCIPSUEnable(unsigned int ci_reg_base,  XLLP_BOOL_T enable);

// Compand and Gamma Correction (CGU) related functions
typedef enum {
    XLLP_CI_CGU_MUX_0_TO_7  = XLLP_CI_CICCR_SCALE_0_TO_7,    // for 8bit raw data
    XLLP_CI_CGU_MUX_1_TO_8  = XLLP_CI_CICCR_SCALE_1_TO_8,    // for 9bit raw data
    XLLP_CI_CGU_MUX_2_TO_9  = XLLP_CI_CICCR_SCALE_2_TO_9     // for 10bit raw data
} XLLP_CI_CGU_MUX_SEL_TYPE;

XLLP_STATUS_T XllpCICGUSetAddrMuxSelect(unsigned int ci_reg_base, XLLP_CI_CGU_MUX_SEL_TYPE mux_select);

typedef enum {
    XLLP_CI_CGU_LUT_RED      = XLLP_CI_CICCR_CLUT_RED,
    XLLP_CI_CGU_LUT_BLUE     = XLLP_CI_CICCR_CLUT_BLUE,
    XLLP_CI_CGU_LUT_GREEN    = XLLP_CI_CICCR_CLUT_GREEN
} XLLP_CI_CGU_LUT_TYPE;

XLLP_STATUS_T XllpCICGULoadLutRam(
                    unsigned int   ci_reg_base,
                    unsigned int   ost_reg_base, 
                    unsigned int  *histogram_lut_buffer_virtual, 
                    unsigned int   histogram_lut_buffer_physical,
                    unsigned int  *histogram_lut_dma_descriptors_virtual, 
                    unsigned int   histogram_lut_dma_descriptors_physical, 
                    unsigned char *lut_ram);

XLLP_STATUS_T XllpCICGUSetBlackLevel(unsigned int ci_reg_base, unsigned char black_level);

XLLP_STATUS_T XllpCICGUEnable(unsigned int ci_reg_base, XLLP_BOOL_T enable);

// Spatial Scaling Unit(SSU) related functions
typedef enum {
    XLLP_CI_SSU_SCALE_DISABLE   = XLLP_CI_CISSC_SCALE_DISABLE,   // disabled
    XLLP_CI_SSU_SCALE_HALF      = XLLP_CI_CISSC_SCALE_2_TO_1,    // 2:1
    XLLP_CI_SSU_SCALE_QUARTER   = XLLP_CI_CISSC_SCALE_4_TO_1     // 4:1
} XLLP_CI_SSU_SCALE;

#define XLLP_CI_SSU_SCALE_DEFAULT XLLP_CI_SSU_SCALE_DISABLE

XLLP_STATUS_T XllpCISSUSetScale(unsigned int ci_reg_base, XLLP_CI_SSU_SCALE scale);

// Color Synthesis Unit(CSU) related functions

// Color Management Unit(CMU) related functions
typedef enum {
    XLLP_CI_CMU_DISABLE    = XLLP_CI_CICMR_DMODE_DISABLE,
    XLLP_CI_CMU_OUTPUT_RGB = XLLP_CI_CICMR_DMODE_RGB,
    XLLP_CI_CMU_OUTPUT_YUV = XLLP_CI_CICMR_DMODE_YUV
} XLLP_CI_CMU_USAGE;

typedef struct
{
    signed short k00, k01, k02;
    signed short k10, k11, k12;
    signed short k20, k21, k22;
} XLLP_CI_CMU_COE_MATRIX;

// just for debug use, will be removed later
#define YUV_FLOAT_TO_INT(x) ((signed short)((float)x*(1UL << 7)) & 0x3ff)
/* example:
static XLLP_CI_CMU_COE_MATRIX cRGB24_to_YUV422_matrix = {
    YUV_FLOAT_TO_INT(0.257) , YUV_FLOAT_TO_INT(0.504) , YUV_FLOAT_TO_INT(0.098),
    YUV_FLOAT_TO_INT(-0.148),  YUV_FLOAT_TO_INT(0.291), YUV_FLOAT_TO_INT(0.439),
    YUV_FLOAT_TO_INT(0.439) , YUV_FLOAT_TO_INT(0.368) , YUV_FLOAT_TO_INT(0.071)
};
*/

// just for debug use, will be removed later
#define RGB_FLOAT_TO_INT(x) ((signed short)((float)x*(1UL << 7)) & 0x3ff)
/* example:
static XLLP_CI_CMU_COE_MATRIX cRGB24_to_sRGB24_matrix = {
    RGB_FLOAT_TO_INT(1.780214),  RGB_FLOAT_TO_INT(-0.96883), RGB_FLOAT_TO_INT(0.188617),
    RGB_FLOAT_TO_INT(-0.7987) ,  RGB_FLOAT_TO_INT(1.790752), RGB_FLOAT_TO_INT(0.007949),
    RGB_FLOAT_TO_INT(-0.67645),  RGB_FLOAT_TO_INT(-1.60901), RGB_FLOAT_TO_INT(3.285467)
};
*/

XLLP_STATUS_T XllpCICMUSetColorCorrectionCoe(unsigned int ci_reg_base, XLLP_CI_CMU_COE_MATRIX *coe_matrix);

XLLP_STATUS_T XllpCICMUEnable(signed int ci_reg_base, XLLP_CI_CMU_USAGE cmu_usage);


//-------------------------------------------------------------------------------------------------------
//      CI dedicated DMAC APIs
//-------------------------------------------------------------------------------------------------------
typedef enum {
    XLLP_CI_DMA_CHANNEL_0 = 0,
    XLLP_CI_DMA_CHANNEL_1,
    XLLP_CI_DMA_CHANNEL_2,
    XLLP_CI_DMA_CHANNEL_3
} XLLP_CI_DMA_CHANNEL;

typedef struct 
{
    XLLP_VUINT32_T   ddadr;  // descriptor address reg
    XLLP_VUINT32_T   dsadr;  // source address register
    XLLP_VUINT32_T   dtadr;  // target address register
    XLLP_VUINT32_T   dcmd ;  // command address register
}XLLP_CI_DMAC_DESCRIPTOR_T, *P_XLLP_CI_DMAC_DESCRIPTOR_T;

#define XLLP_CI_DMAC_DCMD_LEN                  ( 1UL << 0  )
#define XLLP_CI_DMAC_DCMD_EOF_IRQ_EN           ( 1UL << 21 )
#define XLLP_CI_DMAC_DCMD_SOF_IRQ_EN           ( 1UL << 22 )
#define XLLP_CI_DMAC_DCMD_INC_TRG_ADDR         ( 1UL << 30 )


XLLP_STATUS_T XllpCIDMALoadDescriptor(unsigned int ci_reg_base, unsigned int dma_desc_phy, XLLP_CI_DMA_CHANNEL channel);

XLLP_STATUS_T XllpCIDMASetBranch (
           unsigned int ci_reg_base, 
           unsigned int branch_to_dma_desc_phy, 
            XLLP_BOOL_T branch_int_enable, 
            XLLP_BOOL_T branch_after_cur_frame,  
    XLLP_CI_DMA_CHANNEL channel);

//-------------------------------------------------------------------------------------------------------
//      CI/GCU/LCD synchronization APIs
//-------------------------------------------------------------------------------------------------------
typedef enum {
    XLLP_CI_LCD_HANSHAKING_DISABLED  = XLLP_CI_CICR0_LCD_MODE_DISABLED,
    XLLP_CI_LCD_BASE_LAYER           = XLLP_CI_CICR0_LCD_MODE_BASE,
    XLLP_CI_LCD_OVERLAY1_LAYER       = XLLP_CI_CICR0_LCD_MODE_OVERLAY1,
    XLLP_CI_LCD_OVERLAY2_LAYER       = XLLP_CI_CICR0_LCD_MODE_OVERLAY2
} XLLP_CI_SYNC_TO_LCD_TYPE;

XLLP_STATUS_T XllpCISyncToLCD(unsigned int ci_reg_base, XLLP_CI_SYNC_TO_LCD_TYPE lcd_layer_type);

 
#ifdef __cplusplus
}
#endif

#endif


